FIG. 1 is a conceptional diagram of the variable length instruction format. This FIG. 1 indicates that an instruction for the microprocessor is formed by the N areas in maximum. Such an instruction is decoded in a plurality of cycles. The basic area of each part includes an instruction code and the extensible area includes an immediate data. For instance, existence of successive extensible areas and significance of the basic area of the second part are defined on the basis of 16 bits and is located immediately after the operand designation area to extend the operand designation area. The extensible area includes an information for indicating the existence or non-existence of the successive extensible areas. 16*n (n is an integer including 0) indicates that the length of the extensible area is variable in units of 16 bits. In the case of a reduction type, the bit length of the ordinary type operand designation area is reduced by two bits in order to improve execution speed. In such a variable length instruction format, an instruction having a high frequency of use is assigned on the basis of one operand and an instruction having a low frequency of use is assigned on the basis of two or more operands. Thereby, the instructions having a high frequency of use are executed within a short period of time and a kind of instruction can also be increased. An example of such variable length instructions is shown in FIG. 3A to FIG. 3C.
FIG. 3A, FIG. 3B indicate examples of the instruction with two operands format and FIG. 3C indicates an example of the instructions with a one operand format. FIG. 3A indicates an ordinary type instruction of two operands having the effective address field of 8 bits. In this case, the first basic area of 16 bits comprises an instruction code OP, a source operand size SS and a source.operand.effective address eas, while the second basic area comprises an instruction code OP, a destination.operand.size DD and destination.operand.effective address ead. Here, exp 16/32 indicates an extensible area of 16 bits or 32 bits. FIG. 3B indicates an 8 bit.immediate type instruction. The first basic area comprises an instruction code OP and an immediate data #, while the second basic area comprises an instruction code, a destination.operand.size DD and a destination.operand. effective address ead. In this instruction, the extensible area exp 16/32 is added only to the second basic area. FIG. 3C indicates a reduction type instruction to be transferred between the register and memory, comprising the basic area consisting of an instruction code OP, a register designation area R.sub.n, a source.operand.size SS, a source.operand.effective address or a destination.operand.effective address eas/ead and the extensible area exp 16/32.
As the decoding sequence of such a variable length instruction, a stage transition shown in FIG. 4 can be considered. FIG. 4 shows a stage transition diagram of decoding for the instruction comprising three basic areas in maximum. The circle indicates the decoding stage of each area, while the arrow mark indicates the state transition to the other decoding stage. In case the instructions having only the first basic area continues, it is enough to repeat only the decoding stage for the first basic area, but in case an instruction comprises the second and third basic areas and the first, second and third extensible areas, the decoding sequence is complicated for the trial of decoding in the successive stages by simply making reference to the preceding decoding stage because the significance of the instruction code of the successive basic areas changes and the length of the extensible area is also variable due to the instruction code of the first basic area.
For instance, for the decoding of the instruction shown in FIG. 1, the first basic area is decoded and it is decided from the result of decoding that the first extensible area is present. Next, the first extensible area is decoded and when it is decided, as a result of decoding, that the extensible area continues, the decoding process for the first extensible area is repeated. When the decoding of the first extensible area is completed and it is decided, as a result of decoding for the first basic area, that the second basic area is used, the processing transits to the decoding stage of the second basic area. When the second basic area is decoded and it is decided, from the result of decoding for the second basic area, that the second extensible area is used, the processing transits to the decoding stage of the second extensible area. Thereafter, when it is decided, from the result of decoding for the second basic area, that the third basic area is used, the processing transits to the decoding stage of the third basic area. When it is decided, from the result of decoding for the third basic area, that the third extensible area is used, the third extensible area is decoded. When it is decided, from the result of decoding for the third basic area, that the third extensible area and the fourth extensible area are not used, the processing shifts to the next instruction and the decoding is carried out in a decode sequence similar to that explained above. However, such a decoding sequence will be required for shifting to the decoding of the next basic area upon completion of the decoding of each extensible area to confirm that the extensible area in question is associated with which basic area and know the result of decoding of such a basic area. The more the state transition exists, the more the control signal for indicating the transition is necessary. Therefore, the decoding sequencer for stage transition shown in FIG. 4 presents a problem in that the circuit structure is more complicated. This problem becomes more serious as the number of basic areas and extensible areas forming the one instruction increases. In addition, complicated decoding sequencer makes the required time longer for decoding.